The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventor, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Computing devices typically include circuit blocks that perform predetermined functions. Depending on functions performed by a computing device at a given time, a circuit block may or may not be in use at the given time. The unused circuit block, however, may continue to consume power. Power gating and/or clock gating are some of the techniques used to control power consumed by unused circuit blocks.
Power gating is a technique used to reduce leakage power. Unused circuit blocks are temporarily shut down (i.e., turned off) to reduce the overall leakage power. The temporary shutdown is called a low power mode or an inactive mode. When the circuit blocks are required for operation again, the circuit blocks are turned on (i.e., activated to an active mode). These two modes are switched at appropriate times and in a suitable manner to maximize power performance while minimizing impact on speed performance.
Clock gating is a power-saving technique used in synchronous circuits. In synchronous circuits, a clock distribution network distributes one or more clock signals from a common point to all the elements that use the one or more clock signals. When the clock distribution network forms a tree, the clock distribution network is called a clock tree.
To save power, clock gating logic is added to a clock tree. The clock gating logic disables circuits by turning off clock supply to the circuits so that flop-flops in the circuits do not change state. Power that would otherwise be consumed due to switching of the flip-flops reduces to nearly zero, and only leakage currents are incurred.
Generally, if the clock gating logic is not used, circuit elements such as multiplexers can be used to control clock distribution. These circuit elements, however, require additional control logic. These circuit elements and associated control logic dissipate additional power and occupy additional area on a chip.
In contrast, the clock gating logic dissipates less power and occupies less area on a chip than circuit elements such as multiplexers and associated control logic. can be used. Accordingly, to save power and chip area, clock gating can be used instead of multiplexers and associated control logic.